A PLL circuit configured to synchronize the phase of an output clock signal with the phase of an inputted reference clock signal so as to output the synchronized output clock signal from a voltage controlled oscillator (VCO) is used in various fields. The PLL circuit decreases the frequency of the output clock signal when the phase of the output clock signal is advanced with respect to the phase of the reference signal. The PLL circuit increases the frequency of the output clock signal when the phase of the output clock signal is delayed from the phase of the reference signal. Thereby, the PLL circuit adjusts the phase of the output clock signal to the phase of the reference clock signal so as to make the frequency of the output clock signal locked (converged) to a target frequency.
As the PLL circuit, various circuit configurations for reducing the locking time and the jitter have been proposed. For example, a configuration provided with a plurality of charge pump circuits has been proposed (see, for example, Japanese Laid-Open Patent Publication No. 6-276090, Japanese Laid-Open Patent Publication No. 2000-13222, and Japanese Laid-Open Patent Publication No. 10-340544). For example, the PLL circuit described in Japanese Laid-Open Patent Publication No. 6-276090 is provided with a charge pump circuit different from an ordinary charge pump circuit in addition to the ordinary charge pump circuit. Further, the PLL circuit operates the ordinary charge pump circuit and the different charge pump circuit at the time of locking up (the period until the frequency is locked) so as to allow a capacitor of a loop filter to be charged/discharged at high speed. After the locking, the PLL circuit operates only the ordinary charge pump circuit, and sets the different charge pump circuit in the off-state. In this way, the PLL circuit is configured to reduce the locking time and to suppress the noise after the locking.
As described above, in the PLL circuit described in Japanese Laid-Open Patent Publication No. 6-276090, the change in the charge pump current at the time of locking-up is made larger than the change in the charge pump current during the ordinary operation (after the locking) to thereby reduce the locking time and suppress the variation of one period, that is, so called the period jitter, in the output clock signal after the locking. Here, as the jitter to be taken into consideration in the clock signal outputted by the PLL circuit, there is the long term jitter in addition to the period jitter.
The long term jitter is the jitter which occurs in the output clock signal over a long period after the locking. The maximum and minimum values of the time from a certain clock cycle to the other clock cycle separated from the certain clock cycle for a fixed period of time (which is sufficiently longer than the period of the output clock signal) are set as TL and TS, respectively. The long term jitter is represented by (TL-TS) (see FIG. 10).
As a method for suppressing the long term jitter of the clock signal outputted by the PLL circuit, it is considered to set the loop band in the PLL circuit to be wide. For example, it is possible to expand the loop band by increasing the change in the charge pump current with respect to the phase difference between the reference clock signal and the output clock signal without changing the other parameters. However, when the change in the charge pump current with respect to the phase difference is increased, the change in the input voltage of the VCO corresponding to the phase difference is also increased, and thereby the change in the frequency of the output clock signal with respect to the phase difference is increased. In general, the phase difference at the time of locking-up (particularly in the initial stage of the locking operation) becomes larger than the phase difference after the locking. Thus, when the change in the charge pump current with respect to the phase difference is increased, the overshoot at the time of locking-up is caused to greatly exceed an allowable limit in some cases. This prevents the normal operation of the circuit so that the frequency of the clock signal cannot be locked to the target frequency.